AI that matters, from the architect's desk. Curated and engineered by Saaket Varma, PhD — no hype, just signal.
Today's stories map four challenges: access to quantum foundries, conditional public funding, industrial chip validation, and faster circuit generation.
HOW TO READ THIS Read downward from Commerce through the finalized $1B CHIPS award to Anderon’s quantum wafer manufacturing R&D and its intended expansion of wafer access.
Anderon, an IBM company, announced on September 16 that it finalized a $1 billion CHIPS award with the Commerce Department. It also says its first quantum wafers are moving through its 300 mm foundry. This leads today's issue because manufacturing access is a practical constraint on scaling quantum hardware.
The agreement converts May's letter of intent between Commerce and IBM into a finalized award. Anderon fabricates specialized wafers for superconducting-qubit arrays, quantum input/output and readout components, serving customers across the industry. The funding supports research, development and broader access to that manufacturing technology.
For processor developers, shared fabrication could reduce the need to build dedicated manufacturing infrastructure. The concrete advance is finalized funding alongside initial wafer runs. IBM's manufacturing expertise could give Anderon an advantage in attracting customers, if it translates into reliable output. The issuer announcement supplies no production-yield or fault-tolerant-system results, so large-scale computational capability remains a future outcome.
HOW TO READ THIS DOE invites fault-tolerant systems meeting two joint technical targets. Funding is planned up to $215 million, with future appropriations required.
The Department of Energy launched Quantum Genesis Q on September 17, proposing up to $215 million in funding. Companies are invited to demonstrate scientifically useful, fault-tolerant quantum computers. It earns a place here because the competition sets measurable targets for reliable computation.
Applicants must target at least 100 logical qubits, protected by error correction, and hundreds of millions of fault-tolerant operations. Phase I offers up to $1.5 million per awardee for early milestones. Phase II proposes a $100 million pool for qualifying 100-logical-qubit systems, plus separate $50 million pools for demonstrations reaching 150 and 200 logical qubits.
That structure connects funding to capabilities needed for chemistry, materials and other scientific workloads. Its distinctive feature is the combination of logical-qubit capacity, sustained operations and milestone incentives. Suppliers able to demonstrate those capabilities could gain a stronger position in federal quantum programs. This is a competition launch: only $2.5 million is identified in fiscal 2026 dollars, with outyear funding contingent on congressional appropriations and performance still to be demonstrated.
HOW TO READ THIS Read downward from Quobly’s industrial silicon process to gates and readout on one QSOI chip, then to the performance metrics awaiting publication.
Quobly reports qubit readout plus single- and two-qubit gates on one QSOI chip. The devices came from STMicroelectronics' commercial 300 mm manufacturing facilities in Crolles, France. I selected this result because it tests whether essential quantum functions survive transfer into an industrial semiconductor process.
The platform uses silicon spin qubits and FD-SOI CMOS fabrication. Single-qubit gates manipulate individual states, two-qubit gates couple qubits, and readout measures the resulting states. Quobly says it demonstrated all three functions on the same chip, providing initial evidence for its manufacturing approach.
That matters because scaling requires a process that can repeatedly produce usable quantum devices. The specific contribution is combining these operations on a chip fabricated through the industrial process. Existing semiconductor infrastructure could offer an advantage in manufacturing repeatability and cost, although neither advantage is established by this announcement. Detailed performance metrics await a scientific publication; cloud access by the end of 2026 and one million qubits by 2032 remain roadmap targets.
HOW TO READ THIS A trained transformer generates quantum circuits. The benchmark compares roughly28 seconds across tested sizes with over11 minutes of iterative tuning at12qubits; all circuits ran in simulation.
An ORNL-led team with IonQ, NVIDIA and the University of Tennessee, Knoxville evaluated a transformer that generates quantum optimization circuits. Their DQAOA-GPT paper won a Best Paper award at IEEE Quantum Week. I selected it because it tests a specific use of AI inside quantum computing: reducing circuit-search overhead.
The transformer learned from near-optimal circuits produced by conventional iterative tuning. For each subproblem, it generated ten candidates, simulated them and kept the best. Circuit-finding stayed near 28 seconds across tested sizes; iterative tuning exceeded 11 minutes at 12 qubits. Every circuit ran in simulation on one NVIDIA H200 GPU, using cuQuantum through CUDA-Q.
Faster circuit search could make hybrid optimization easier to explore. The distinctive change replaces repeated parameter adjustment with learned generation and a fixed number of candidate evaluations. A potential advantage is lower recurring search overhead once the model is trained. This is benchmark-scale validation comparing two quantum circuit-generation workflows, with no QPU execution or demonstrated advantage over classical solvers.
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